The present invention relates generally wafer level processing of integrated circuits. More particularly, a wafer level packaging arrangement is described that permits parameter trimming and final testing to be accomplished during a single probing sequence.
A variety of semiconductor devices (particularly precision analog semiconductor devices) require that the circuits be trimmed after fabrication. Generally, trimming is the process of fine-tuning the performance of an integrated circuit device after fabrication in order to ensure conformance to a desired performance specification. In order to facilitate trimming, it is common to provide metal pads, often referred to as “trim pads” on the active surface of the die. Generally, a specific current is applied to each trim pad at a specific voltage in order to activate components (e.g. fuses) that can adjust the performance of the circuits of interest.
There are a number of conventional processes for packaging integrated circuits. One approach that is commonly referred to as “flip chip” packaging generally contemplates forming solder bumps (or other suitable contacts) directly on the face of an integrated circuit die. In some situations, the contacts are formed directly on I/O pads formed on the die, whereas in other situations the contacts are redistributed. The die is then typically attached to a substrate such as a printed circuit board or a package substrate such that the die contacts directly connect to corresponding contacts on the substrate.
When trim pads are included in flip chip package designs (or other wafer level chip scale packages) it is common to deposit a passivation material over the trim pads after the device has been trimmed. By way of example, a representative process might proceed as illustrated in FIG. 5. Specifically, after the wafer is fabricated (302), the wafer is taken to a wafer prober which tests and trims the appropriate circuits (304). The trim pads are generally formed from aluminum and thus they will corrode if left exposed in an ambient environment. Also, if they are left exposed when the singulated die is soldered to a substrate, there is a significant risk that the solder may bridge the gap between one of the bond pad/trim pad pairs, thereby shorting out the die. To avoid these problems, some manufacturing approaches contemplate covering the trim pads with a passivation material after the wafer has been trimmed. This helps reduce corrosion of the trim pads but requires returning to the wafer to the wafer processing chamber where a passivation layer (e.g. polyimide or benzocyclobutene (BCB)) is applied over the trim pads (306). Typically, the passivation layer also extends over edge portions of the I/O pads as well. Thus, the passivation layer is used to isolate the trim pads.
After the passivation layer is applied, appropriate underbump metallization stacks are typically formed on the I/O pads (308) and the wafer is bumped (310). It should be appreciated that there may be a number of other processing steps that occur before, as part of, or after the bumping. When the desired processing is completed, the wafer is again taken to a wafer prober where the final testing occurs.
In this scenario, wafer probe testing must be done twice. Initially, the wafer must be probed to facilitate trimming, which must occur before the trim pads are insulated by the passivation material. The wafer must also be probed a second time to test for electrical function after the contact bumps have been placed on the dies. Although the described process works well, this two-part wafer probing process is inefficient, since the wafer must go to a testing facility for trimming, and subsequently, to a manufacturing facility to cover the trim pads and then back to the testing facility for the final wafer probing before the dies are cut and shipped to customers. These inefficiencies add to the overall cost of manufacturing these IC devices. Therefore, there are continuing efforts to reduce the costs and time associated with the manufacturing process.